module top_module (
    input clk,
    input reset,   // Synchronous active-high reset
    output [3:1] ena,
    output [15:0] q);

//    reg	[13:0]	cnt;
    
    always @(posedge clk) begin
        if(reset) begin
            q[3:0] <= 4'd0;
        end
        else begin
            if(q[3:0] == 4'd9) begin
                q[3:0] <= 4'd0;
            end
            else begin
                q[3:0] <= q[3:0] + 1'b1;
            end
        end
    end
    
    always @(posedge clk) begin
        if(reset) begin
            q[7:4] <= 4'd0;
        end
        else begin
            if((q[7:4] == 4'd9) && (ena[1])) begin
                q[7:4] <= 4'd0;
            end
            else begin
                q[7:4] <= q[7:4] + ena[1]; 
            end
        end
    end
    
	always @(posedge clk) begin
        if(reset) begin
            q[11:8] <= 4'd0;
        end
        else begin
            if((q[11:8] == 4'd9) && (ena[2])) begin
                q[11:8] <= 4'd0;
            end
            else begin
                q[11:8] <= q[11:8] + ena[2]; 
            end
        end
    end
    
    always @(posedge clk) begin
        if(reset) begin
            q[15:12] <= 4'd0;
        end
        else begin
            if((q[15:12] == 4'd9) && (ena[3])) begin
                q[15:12] <= 4'd0;
            end
            else begin
                q[15:12] <= q[15:12] + ena[3]; 
            end
        end
    end
    
    assign ena[1] = (q[3:0] == 4'd9);
    assign ena[2] = (q[7:4] == 4'd9) && ena[1];
    assign ena[3] = (q[11:8] == 4'd9) && ena[2];
    
endmodule
